A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance. (March 2020)

• Record Type: Journal Article
• Authors: Nayak, Debasish; Rout, Prakash Kumar; Sahu, Sudhakar; Acharya, Debiprasad Priyabrata; Nanda, Umakanta; Tripthy, Dhananjaya
• Is Part Of: Microelectronics journal. Volume 97(2020)
• Publication Date: 2020-03
• Subjects: Charge recycling -- Indirect read -- Half-selected cell -- Single ended write -- SRAM -- Leakage current; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104723
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Read noise insertion problem of conventional read method of 6T-SRAM cell has forced to think about indirect read. Indirect read though eliminates read noise insertion but also take away the capability to use differential sensing thus leading to more energy and time consumption. Charge recycling concept must be followed by the SRAM cell to reduce energy consumption. An indirect read technique based SRAM is proposed which is capable to follow differential sensing along with following charge recycling technique. Thus it makes the proposed SRAM cell high stable, fast and low energy consuming. Theoretical estimation states that write and read energy consumption of the proposed cell is 12.5% and 25% smaller than those of the compared RDFD-SRAM. Stability analysis shows that the read SNM of the proposed cell which is the most critical stability index is same as its retention SNM and is 317% of the read SNM of conventional 6T-SRAM. The delay analysis also states the fastness of proposed cell. Highlights: An indirect read technique based SRAM is proposed in this work which eliminates the read noise insertion problem. This cell also follows differential sensing mechanism during read operation to maintain high speed. During read operation it recycles the charge content of read bit line with the write bit line instead of discharging to ground leading to reduction of energy consumption. An empirical formulation is designed to theoretically estimate the write energy consumption required to write a particular data after reading and writing to the same column. Similarly another empirical formulation is designed to theoretically estimate the read energy consumption required to read a particular data consecutively after reading another data from the same column. The theoretical estimation states that the write and read energy consumption of the proposed cell is 12.5% and 25% smaller than those of the compared RDFD-SRAM. Experimental simulation using predictive technology model demonstrates that, the write and read energy consumptions are reduced by 10.9% and 24.57% respectively. The leakage current flow in the standby cells of the proposed SRAM array is also reduced. The energy consumption in the half-selected cells is also reduced significantly. The most critical stability index, i.e. the read SNM of the proposed cell is same as its retention SNM and is 317% of the read SNM of the conventional 6T-SRAM cell.