Power and performance analysis of 3D network-on-chip architectures. (May 2020) - Halavar, Bheemappa; Talawar, Basavaraj
Highlights: Explored the design space of 3D NoCs using floorplan driven wire lengths and link delay estimation. TSV based power and delay model have been extended to a cycle accurate simulator to estimate accurate power and performance of 3D NoC architecture and analysed the topologies for power, performance and cost trade-offs of 3D variants of the Mesh and BFT topologies. The behavior of 2D and 3D NoC variants are observed by varying buffer space, and 3D variants are evaluated based on equalised buffer space to 2D Mesh topology and data serialization over TSVs to reduce the TSV are by 50%. Using the extended 3D TSV modules, performance (average network latency), and energy efficiency metrics (Energy-Delay Product) of variants of 3D Mesh and 3D Butterfly Fat Tree topologies have been evaluated using two synthetic traffic patterns. Graphical abstract: Abstract: Emerging 3D integrated circuits(ICs) employ 3D network-on-chip(NoC) to improve power, performance, and scalability. The NoC Simulator uses the microarchitecture parameters to estimate the power and performance of the NoC. We explore the design space for 3D Mesh and Butterfly Fat Tree(BFT) NoC architecture using floorplan drive wire length and link delay estimation. The delay and power models are extended using Through Silicon Via (TSV) power and delay models. Serialization is employed to reduce the TSV area cost. Buffer space is equalised for a fair comparison between topologies. The Performance, Flits per Joules(FpJ) and Energy Delay Product(EDP) of six 2D and 3D variants of Mesh and BFT topologies (two and four layers) are analyzed by injecting synthetic traffic patterns. The 3D-4L Mesh exhibit better performance, energy efficiency (up to 4.5 × ), and EDP (up to 98 %) compared to other variants. This is because the overall length of the horizontal link is short and the number of TSVs is large (3 × ).