Design options for implementing in standard CMOS drivers for MEMS body biasing. (March 2020) - Miresan, Paul; Onet, Raul; Neag, Marius; Topa, Marina; Chira, Cosmin
Abstract: This paper presents design options and transistor-level solutions for implementing, in CMOS processes without triple-well, drivers suitable for MEMS body biasing. The output voltage of the driver envisaged here can be set to positive or negative levels, programmable between (+10 ​V to +20 ​V), respectively (−20 ​V to −10 ​V), with a resolution of 100 ​mV. Also, the driver can ground its output terminal, as well as leave it open/floating, all under digital control. The key parts of such a driver are the voltage generators that provide positive and negative voltages several times larger than the supply voltage and the output stage that delivers the voltage required to bias the MEMS body terminal, VMEMS . Three solutions, which consist of driver topology and circuit implementation of key elements, are proposed and analyzed comparatively. The first solution requires the development of one ASIC that comprises a 9-bit DAC, as well as drivers for the digitally-programmable voltage generators – a boost DC-DC converter and an inverting (negative output voltage) charge pump – which provide directly the wanted positive or negative VMEMS voltage levels, while the output stage is a voltage multiplexer implemented with high-voltage external transistors. The second solution requires two ICs that operate at different substrate voltage levels: an ASIC comprising the same DAC but simpler drivers for more compact, but less accurate, voltage generators. This time, the large positive and negative voltages are only used to supply the output stage of the system. Two options are presented for the later: an off-the-shelf IC and an ASIC that implements a single-OpAmp differential amplifier with positive/negative gain set digitally. The third solution is a more versatile version of the same approach, whereby the first ASIC implements only the positive and negative voltage generators that supply the second ASIC, which comprises a 7-bit DAC and a digitally configurable amplifier. One instance of the first ASIC can supply multiple instances of the second ASIC that operate in parallel, under common or individual control. Proof-of-concept implementations of the proposed ASICs were designed in a high-voltage 0.18 ​ ​μm CMOS process without triple well; schematics of key blocks are presented in the paper. Simulation results validate the design, demonstrating that it is indeed possible to implement in standard CMOS all the circuit functions mentioned above, while reducing the number of external components to a minimum.