A high-performance framework for a network programmable packet processor using P4 and FPGA. (15th April 2020) - Yazdinejad, Abbas; Parizi, Reza M.; Bohlooli, Ali; Dehghantanha, Ali; Choo, Kim-Kwang Raymond
Abstract: The emergence of new network technologies and users' ever-increasing demand necessitates the introduction of highly programmable hardware with high flexibility and performance at the network data plane. The switches at the data plane need to be flexible enough to support protocols and test new ideas for increasing the abstraction of network programming. In most studies, Field Programmable Gate Arrays (FPGA) are applied in making switches flexible and reprogrammable; however, applying FPGAs alone does not meet the required flexibility. Next to applying FPGAs, it is necessary to provide an architecture that would allow developers to forego FPGA implementation hardware details and the complexity of hardware description language (HDL). In this paper, a new architecture of a programmable packet processor with high flexibility and programmability at the network data plane is presented, which supports all three operations required in switches: parsing, classification, and processing of packet data. To implement this architecture, the high-level P4 language is applied to allow the description of its register-transfer level (RTL) on the FPGA. In order to increase the processing speed, a pipeline approach within the proposed architecture is designed at the SDN data plane through pre-processing in the parse graph, identifying the traffic flow, and applying the hybrid control flow model in the data processing. The results show that our architecture operates at 320 MHz clock speed, which in comparison with NetFPGA-10G, NetFPGA-SUME, and ML605 peer architectures runs 2, 1.28, and 2.9 times faster in terms of processing speed, attesting to its efficiency. In addition, the evaluation on the Virtex-7 FPGA VC709 platform shows that our architecture consumes approximately 4.3% of lookup tables, 1.9% of flip-flops, and 1.3% of memory blocks, which are less than the hardware resource consumption of peer architectures. Highlights: High-performance framework for a network programmable packet processor. Architecture for parsing, classification and processing of packet data. Work around FPGA implementation hardware details, and complexity of HDL.