A 0.18 μm CMOS capacitor-less Low-Drop Out Voltage Regulator Compensated via the Bootstrap Flipped-Voltage Follower. (July 2020) - Zamora-Mejia, Gregorio; Gomez-Garcia, Dario Edwin; Giron-Nieto, Huber; Martinez-Castillo, Jaime; Moreno-Coria, Luis Armando; Rocha-Perez, Jose Miguel; Diaz-Sanchez, Alejandro
Abstract: This work presents a Cap-less Low-Drop Out (LDO) Voltage Regulator that uses a Bootstrap Flipped-Voltage Follower (B-FVF) as the input stage of its active compensation network. Previous works use active compensation networks whose frequency response shows a high-pass behavior that depends on their compensation capacitor C f . The dominant pole is related to the value of C f . By using the B-FVF, this C f -pole dependency is broken; only the gain of the compensation loop lies on C f, while the high-pass pole is referred to the B-FVF input node capacitance. This advantage allows the integration of a smaller C f, a 10X reduction compared with the state-of-the-art, and easier placement of the high-pass pole to higher frequencies than the LDO open-loop Gain Bandwidth (GBW). The proposed LDO presents a quiescent current consumption of 95  μA at a 1.8 V input voltage, delivering a 0mA–50mA load current at a 1.6 V output voltage. A load and line transient responses of 133 mV and 165 mV were measured by using a C f of only 0.3 pF and a load capacitor C L of 100 pF. In order to validate the proposed LDO, simulations and measurements were performed in 0.18 μm CMOS Standard technology. The silicon area consumption is 0.133 mm 2 .