ChangeSUB: A power efficient multiple network-on-chip architecture. (May 2020)

• Record Type: Journal Article
• Authors: Baharloo, Mohammad; Aligholipour, Rashid; Abdollahi, Meisam; Khonsari, Ahmad
• Is Part Of: Computers & electrical engineering. Volume 83(2020)
• Publication Date: 2020-05
• Subjects: Multiple network-on-chip -- Router architecture -- Low power -- Power gating -- Static power -- Energy proportionality; Computer engineering -- Periodicals; Electrical engineering -- Periodicals; Electrical engineering -- Data processing -- Periodicals; Ordinateurs -- Conception et construction -- Périodiques; Électrotechnique -- Périodiques; Électrotechnique -- Informatique -- Périodiques; Computer engineering; Electrical engineering; Electrical engineering -- Data processing; Periodicals; Electronic journals; 621.302854
• DOI: 10.1016/j.compeleceng.2020.106578
• Languages: English
• ISSNs: 0045-7906

Abstract

Abstract: Applying power gating on network-on-chip (NoC) as an effective static power-aware technique could lead to a significant reduction in on-chip network performance. Since the NoC performance has a considerable impact on the overall chip performance, providing a trade-off between chip power and its performance is crucial. To this end, applying power gating in multiple network-on-chip (multi-NoC) instead of traditional NoC is a promising solution. However, in multi-NoC, waking-up a chain of routers in a switched-off sub-network (subnet) incurs performance penalty. In this paper, we introduce an architecture, namely ChangeSUB, which provides an opportunity to change the subnet of packets in multi-NoC architecture. In the proposed architecture, packets avoid encountering switched-off routers by changing their subnet. Experimental results indicate that compared to traditional multi-NoC design, the proposed architecture decreases the network latency, execution time, and NoC's static power consumption by 10.5%, 4.5%, and 17.6%, respectively, with just imposing 1.9% hardware overhead.