Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. (April 2020)

• Record Type: Journal Article
• Authors: Maiti, M.; Majumder, A.; Chakrabartty, S.; Song, H.; Bhattacharyya, B.K.
• Is Part Of: Microelectronics journal. Volume 98(2020)
• Publication Date: 2020-04
• Subjects: Voltage controlled oscillator -- Low power -- Clock & data recovery -- Phase noise -- Output noise; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104752
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Voltage Control Oscillator (VCO) is a vital block in mobile communication systems as it offers carrier frequency signal or the frequency needed for down conversion of input. The ample blooming in mobile communication has urged for low power VCO to increase the battery lifetime. In this work, we have tendered an ultra-low power design of single ended hybrid Current Starved-CMOS (CS-CMOS) Ring VCO with wide tuning capability. The circuit reads an average power and settling time (delay) of 44.51 ​μW and 8.69ps respectively when simulated for 90 ​nm CMOS using CADENCE Virtuoso platform with a control voltage of 1 ​V and supply voltage of 1.2 ​V. It also offers a phase noise of as low as −111.84 ​dBc/Hz at 1 ​MHz offset and an output oscillation frequency of 2.52 ​GHz. The final physical layout of the proposed circuit estimates an area of 64.279 ​μm 2 . The post-layout analysis has noted an alteration of 3.04%, 3.57%, 117.03% and 1.98% respectively for phase noise, average power, delay and oscillation frequency. The performance metrics also include a wide tuning range of as high as 93.81%, which gets increased by 1.59% during post-layout computation. Corner analyses through 500 runs of Monte-Carlo and validation of functionality in lower process node are performed to prove the robustness and scalability of the proposed circuit. Highlights: The article explores a Hybrid VCO design as a cascaded form of Basic CMOS Inverter and Current Starved Inverter. A Mathematical model of the new design is derived to estimate the oscillation frequency, which shows tiny deviation with computed value. The gain of hybrid VCO is noted to be almost constant beyond Vctrl ​= ​1V. Monte-Carlo with skew/without skew and worst case simulation are carried out with the emulation of effect from power delivery network to justify the reliability of the design. In comparing with current starved VCO, the proposed hybrid design achieves betterment in oscillation frequency, gain, FoM and gate count by 78.98%, 21.31%, 2.04% and 26.09% respectively after giving away a mere penalty of 44.37% in terms of power consumption. The circuit is simulated and validated in lower process nodes like UMC 28 ​nm to prove its worth in terms of scalability with technology trend.