Design of low power fault tolerant flash ADC for instrumentation applications. (April 2020)

• Record Type: Journal Article
• Authors: Prathiba, G.; Santhi, M.
• Is Part Of: Microelectronics journal. Volume 98(2020)
• Publication Date: 2020-04
• Subjects: Offset error -- Power utilization -- Unary code -- Fault tolerant -- Architecture; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104739
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Technological growth has remarkably put their efforts in making the electronic world a powerful one. Analog to digital converter (ADC) is said to be ancestor in the field of transforming analog information into digital form. It is a necessary component in RF and Mixed signal designs. This paper suggests both neither compact NOR based CMOS Linear Tuneable Transconductance Element (NOR-LTE) Comparator and Dynamic Priority Encoder (DPE). The NOR-LTE comparator reduces the power utilization and offset error, which improves the Power Supply Rejection Ratio (PSRR) of an overall circuit design. Dynamic Priority Encoder curtails the transistor count prescribed for Flash ADC. The proposed Fault Tolerant Flash ADC (FT-FADC) framework is implemented using Tanner EDA with 0.25 ​ ​μm CMOS technology. The above suggested FT- FADC achieves 3.44-bit ENOB at 1.5 ​V supply for 500 ​MHz Resolution Bandwidth (RSB). Due to high sampling rate 1.3 ​GS/s it upgrades the throughput rate by 60% and reduces the utilization of power by 47%.