Area-efficient low-latency polynomial basis finite field GF(2m) systolic multiplier for a class of trinomials. (March 2020)

• Record Type: Journal Article
• Authors: Pillutla, Siva Ramakrishna; Boppana, Lakshmi
• Is Part Of: Microelectronics journal. Volume 97(2020)
• Publication Date: 2020-03
• Subjects: Internet of things -- Elliptic curve cryptography -- Finite field arithmetic -- Bit-parallel multiplier -- Systolic architecture; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2020.104709
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: Many security and data reliability algorithms rely heavily on finite field GF(2 m ) arithmetic computations, in particular, multiplication. The design of a field multiplier employing systolic architecture is very much suited for very large scale integration (VLSI) implementation. Though systolic architecture gives higher throughput, it usually requires area overhead and high-latency. In this paper, we propose a systolic architecture for polynomial basis finite field GF(2 m ) multiplier based on a class of trinomials. Analysis shows that the proposed multiplier achieves low-area and low-latency compared to similar multipliers available in the literature. The proposed multiplier achieves 10% reduction in area complexity when compared with the best existing area-efficient multiplier, for m = 409. Application specific integrated circuit (ASIC) implementation of the proposed multiplier together with the two most comparable multipliers confirms that the proposed multiplier outperforms the other two multipliers with improvements in area and latency. The proposed area-efficient multiplier is suitable for Internet of Things edge-devices.