A 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers. Issue 6 (26th May 2020)

• Record Type: Journal Article
• Authors: Kim, Tae‐Jin; Hwang, Jong‐Il; Lee, Sangkyu; Chun, Sengsub; Ryu, Seong‐Young; Lee, Soo‐Joo; Cho, Hyunwoo; Tak, Wonho; Kim, Yong‐Jae; Lee, Hoomin; Pae, Hansu; Lim, Hyun‐Wook; Lee, Jae‐Youl
• Is Part Of: Journal of the Society for Information Display. Volume 28:Issue 6(2020)
• Page Start: 535
• Page End: 547
• Publication Date: 2020-05-26
• Subjects: balanced coding -- clock‐embedded signaling -- clock recovery -- deskew circuit -- display driver -- dual‐mode receiver -- host interface -- MIPI C‐PHY -- MIPI D‐PHY -- tri‐signaling; Information display systems -- Periodicals; 621.38154205
• DOI: 10.1002/jsid.916
• Languages: English
• ISSNs: 1071-0922

Abstract

Abstract: This paper presents a 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers. To reduce size overhead from the dual‐mode interfaces, we propose the termination circuit that shares 50‐Ω terminations and common‐mode capacitors while maintaining a perfectly matched load balance. The proposed dual‐mode receiver can support 14‐Gb/s total bandwidth in each interface mode, resulting in broad compatibility with application processors. A mobile display driver using the proposed dual‐mode receiver is fabricated in a 28‐nm high‐voltage CMOS process and verified up to 3.5 Gb/s per lane in the D‐PHY mode and 2.2 Gs/s per trio in the C‐PHY. Abstract : A 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers is proposed for broad compatibility with application processors. A mobile display driver using the proposed dual‐mode receiver is fabricated in a 28‐nm high‐voltage CMOS process and verified up to 3.5 Gb/s per lane in the D‐PHY mode and 2.2 Gs/s per trio in the C‐PHY.