A low‐power, low‐data‐rate efficient ADC with hybrid exponential‐linear transfer curve for bio‐potential recording systems. (29th February 2020)

• Record Type: Journal Article
• Authors: Gharaei Jomehei, Maryam; Sheikhaei, Samad; Saberi, Mehdi
• Is Part Of: International journal of circuit theory and applications. Volume 48:Number 4(2020)
• Page Start: 449
• Page End: 471
• Publication Date: 2020-02-29
• Subjects: analog‐to‐digital converter -- biomedical‐interface circuits -- bio‐potential recording -- exponential ADC -- low‐power -- multichannel recording -- nonlinear ADC; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2779
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) is presented in this paper, which is attractive, where a high dynamic range (DR) is required. It is especially applicable for sampling neural (bio‐potential) signals, as most of the neural signal data are concentrated on higher side of the amplitude range. By the exponential quantization function for low signal amplitudes, the background noise that disperses in lower amplitudes will be reduced. For higher signal amplitudes, the exponential function optionally switches to linear function at an adjustable voltage threshold, to reduce required number of bits for those high amplitudes, as well. As a result of this exponential‐linear hybrid operation, the total data rate and the power required for data transmission are decreased. A prototype 8‐bit counter‐based exponential ADC is designed and simulated in 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS). The 20‐KS/s ADC achieves a DR of 66 dB, occupies 0.036 mm 2 area, and consumes 6.4‐μW power from a 1.8‐V supply. Integral nonlinearity (INL) and differential nonlinearity (DNL) that are redefined to be compatible with nonlinear ADCs are 3.2 and 0.88 least significant bits (LSBs), respectively. Abstract : A digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) for neural signals are presented. The exponential characterization is chosen to reduce the background noise disperse in lower amplitudes and also the linear one to reduce required number of bits for high amplitudes. By this idea, the total data rate and the power required for data transmission are decreased. The prototype 8‐bit exponential ADC, which is designed and simulated in 0.18‐μm CMOS, consumes only 6.4‐μW power from a 1.8‐V supply at 20 KS/s.