A high power CMOS cascode power amplifier with adaptive dynamic bias control for linearity enhancement. Issue 7 (29th February 2020) - Ren, Jiangchuan; Dai, Ruofan; He, Jun; Zhang, Zhengxuan; Zou, Shichang
Abstract: This work presents both high power and high linearity CMOS cascode power amplifier (PA) with adaptive dynamic bias (ADB) circuit. The ADB circuit sets appropriate gate bias for the common source and common gate (CG) amplifiers according to the input envelope signal, significantly improving the linearity. Meanwhile, harmonic termination circuits are introduced at the gate of the CG amplifier and the center‐tap node of the output transformer to short the second harmonic component to ground, further improving the linearity. In addition, this work utilizes an on‐chip series‐connected transformer‐based power combiner to enhance output power. A fully integrated differential PA including the ADB circuit is fabricated in 0.13 μm radio frequency silicon‐on‐insulator technology. From 2.5 V supply voltage, the proposed PA produces a saturated output power of 30.3 dBm with a peak power‐added efficiency of 43.1%. Thanks to the linearization techniques, the proposed PA transmits 23.5 dBm average linear output power with 3% error vector magnitude for a 20‐MHz 64‐QAM orthogonal frequency division multiplexing modulated signal without any digital predistortion circuits.