Design and simulation of all optical shift registers using D flip‐flop. Issue 7 (29th February 2020)

• Record Type: Journal Article
• Authors: Ramachandran, Manohari; Prince, Shanthi; Kambham, Archana; Maruthi, Naga
• Is Part Of: Microwave and optical technology letters. Volume 62:Issue 7(2020:Jul.)
• Page Start: 2427
• Page End: 2438
• Publication Date: 2020-02-29
• Subjects: all optical logic gates -- all optical shift register -- D flip‐flop -- semiconductor optical amplifier; Microwaves -- Periodicals; Optics -- Periodicals; 621
• DOI: 10.1002/mop.32350
• Languages: English
• ISSNs: 0895-2477

Abstract

Abstract: All optical memory elements are considered to be essential building components for optical networks with high practicality and utility. In this paper, a feasible integrable scheme is presented for the realization of all optical shift register, which is basically a memory device, where the information is transferred from input to output based on the configurations either in serial or parallel upon a clock pulse. Shift registers are classified based on input‐output configuration as serial input‐serial output, serial input‐parallel output, parallel input‐serial output (PISO), and parallel input‐parallel output. All optical shift register is designed using interconnected D flip‐flop (DFF) memories that are driven by standard clock pulses. DFF is built using Mach‐Zehnder interferometer‐semiconductor optical amplifier based on all optical logic gates, which is then cascaded accordingly to design different types of 4‐bit shift registers except for PISO which is designed as a 2‐bit shift register. The entire design is simulated in optisystem and verified the data transfer through DFFs in various configurations. The speed of the circuit is the same as data rate. The proposed circuits are simulated up to data rate of 100 Gbps.