A novel cross‐connected multilevel inverter topology for higher number of voltage levels with reduced switch count. (20th March 2020) - Prem, Ponnusamy; Sugavanam, Vidyasagar; Abubakar, Ahamed Ibrahim; Ali, Jagabar Sathik Mohamed; C Sengodan, Boopathi; Krishnasamy, Vijayakumar; Padmanaban, Sanjeevikumar
Summary: A new basic unit of 25‐level asymmetric multilevel inverter topology is proposed in this article. The extended and cascaded topologies are developed to increase the output voltage level. Furthermore, to determine the magnitude of DC source values in each unit, two algorithms are presented. The proposed extended and cascaded structures are compared with other recent and conventional multilevel inverter topologies in terms of a number of DC sources, blocking voltage on the switches and cost of the inverter. The performance of the proposed topology is validated through the MATLAB/Simulink tool and laboratory setup for 25‐level output. The dynamic performances of proposed topology is confirmed with different loading conditions and their results are presented.