Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips. (7th January 2020)

• Record Type: Journal Article
• Authors: Fan, Weibei; He, Jing; Han, Zhijie; Li, Peng; Wang, Ruchuan
• Is Part Of: Concurrency and computation. Volume 32:Number 11(2020)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2020-01-07
• Subjects: fault tolerance -- graph embedding -- network‐on‐Chip -- reconfigurable -- wirelength; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.5659
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Network‐on‐chip (NoC) is a new design method of system‐on‐chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n ‐cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n ‐cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault‐tolerant layout of incomplete ternary n ‐cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area.