Integration of perovskite Pb[Zr0.35Ti0.65]O3/HfO2 ferroelectric-dielectric composite film on Si substrate. Issue 3 (4th June 2020)

• Record Type: Journal Article
• Authors: Singh, Prashant; Jha, Rajesh Kumar; Goswami, Manish; Singh, B.R.
• Is Part Of: Microelectronics international. Volume 37:Issue 3(2020)
• Page Start: 155
• Page End: 162
• Publication Date: 2020-06-04
• Subjects: Endurance -- Fatigue -- Ferroelectric -- Memory window -- Metal-ferroelectric-insulator-silicon -- Plasma-enhanced atomic layer deposition; Microelectronics -- Periodicals; 621.381
• DOI: 10.1108/MI-11-2019-0069
• Languages: English
• ISSNs: 1356-5362

Abstract

Abstract : Purpose: The purpose of this paper is to investigate the effect of high-k material HfO2 as a buffer layer for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Design/methodology/approach: RF-sputtered Pb[Zr0.35Ti0.65]O3 or (PZT) and plasma-enhanced atomic layer deposited HfO2 films were selected as the ferroelectric and high-k buffer layer, respectively, for the fabrication of metal-ferroelectric-insulator-silicon (MFeIS) structures on Si (100) substrate. Multiple angle ellipsometry and X-ray diffraction analysis was carried out to obtain the crystal orientation, refractive index and absorption coefficient parameters of the deposited/annealed films. In the different range of annealing temperature, the refractive index was observed in the range of 2.9 to 2 and 1.86 to 2.64 for the PZT and HfO2 films, respectively Findings: Electrical and ferroelectric properties of the dielectric and ferroelectric films and their stacks were obtained by fabricating the metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal, metal/insulator/silicon and MFeIS capacitor structures. A closed hysteresis loop with remnant polarization of 4.6 µC/cm 2 and coercive voltage of 2.1 V was observed in the PZT film annealed at 5000 C. Introduction of HfO2 buffer layer (10 nm) improves the memory window from 5.12 V in MFeS to 6.4 V in MFeIS structure with one order reduction in the leakage current density. The same MFeS device was found having excellent fatigue resistance property for greater than 1010 read/write cycles and data retention time more than 3 h. Originality/value: The MFeIS structure has been fabricated with constant PZT thickness and varied buffer layer (HfO2 ) thickness. Electrical characteristics shows the improved leakage current and memory window in the MFeIS structures as compared to the MFeS structures. Optimized MFeIS structure with 10-nm buffer layer shows the excellent ferroelectric properties with endurance greater than E10 read/write cycles and data retention time higher than 3 h. The above properties indicate the MFe(100 nm)I(10 nm)S gate stack as a potential candidate for the FeFET-based nonvolatile memory applications.