An energy-efficient variation aware self-correcting latch. (February 2019) - Kumar, Chaudhry Indra; Sharma, Arvind Kumar; Partap, Rajendra; Bulusu, Anand
Abstract: Power dissipation is a prime concern in sub-nanometer VLSI regime and, therefore, operation at near/sub-threshold regime has gained importance. However, though energy efficient, a system performance/functionality is at stake, because of the increase in the variability in near/sub-threshold regime. Therefore, resilient circuit approaches are important in alleviating the performance degradation resulting from Process, Voltage, and Temperature (PVT) variations. This paper presents an energy efficient and resilient circuit design approach using novel self correcting latches. The proposed technique corrects the faults due to timing violation caused by variations in datapaths and sequential elements automatically, thereby lowering PVT variation induced performance degradation. Our technique employs Inverse Narrow Width Effect (INWE) in designing the self-correcting latches to reduce performance variability. In this technique INWE is used to realize devices which have equal gate capacitances and different current drives. We validate the proposed methodology on several ISCAS′89 benchmark circuits and 74X series circuits. Simulation results show that by employing the proposed methodology, an average improvement of ∼20%, 10%, and 4.85% in delay, power delay product, and layout area, respectively, over previous resilient methodologies can be achieved.