A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. (February 2019)

• Record Type: Journal Article
• Authors: Ni, Zhekan; Chen, Yongzhen; Ye, Fan; Ren, Junyan
• Is Part Of: Microelectronics journal. Volume 84(2019)
• Page Start: 59
• Page End: 66
• Publication Date: 2019-02
• Subjects: SAR ADC -- Asynchronous -- Single-channel -- Control logic -- Unit capacitor; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2018.12.009
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents a 9-bit 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with hybrid arranged capacitor array. High-speed operation is achieved by introducing a redundant weighting method into the hybrid arranged SAR CDAC and using a fast control logic which shorten the critical path. By using a custom-designed unit capacitor which minimizes top plate parasitic capacitance, the SAR ADC can realize a wide input range of 1.6 Vdiff, p-p at 1-V reference voltage. At 400 MS/s sampling rate, the ADC achieves an SNDR of 52.47 dB and consumes 1.19 mW, resulting in a figure of merit (FOM) of 7.8 fJ/conversion-step. The ADC is fabricated in a 28 nm CMOS technology and its core occupies an active area of 171 μm × 112 μm.