An area‐efficient FFT processor for the OFDMA transceiver communication system. (29th November 2018)

• Record Type: Journal Article
• Authors: Nirmala, N.; Sumathi, S.
• Other Names: Karthikeyan M. guestEditor.; Chilamkurti Naveen guestEditor.; Li Xiong guestEditor.
• Is Part Of: Concurrency and computation. Volume 31:Number 14(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-11-29
• Subjects: Fast Fourier Transform (FFT) -- orthogonal frequency‐division multiple access OFDMA) -- very large scale integration (VLSI); Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.4875
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Orthogonal frequency division multiplexing (OFDM) is a well‐organized multiplexing scheme, which is long‐established in recent wireless and communication standards. OFDM resembles a system of exchanging information done with a nonflat channel called Discrete Multi‐Tone modulation (DMT) and Coded OFDM (COFDM). The data stream in this frequency modulation is divided across narrowband channels to limit interference and crosstalk. One of the extreme needs of OFDM is reasonable to be straight mean while sending and receiving systems. OFDM is extremely preferred for rapid data transmission and radio access method. In this paper, OFDM transceiver is carried out and implemented on FPGA. In addition, 128‐point IFFT/FFT pipelined architecture is proposed with the aim of optimizing area, frequency, and circuit complexity.