Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs. Issue 3 (3rd March 2020) - Osipov, Dmitry; Lange, Heiner; Paul, Steffen
ABSTRACT: A new digital delay line based on the inverter chain is proposed. The proposed new method of connection of the inverters allows much longer delay times to be achieved for the same number of transistors, the same amount of power to be consumed as for conventional connection of inverters. Simulation results using a 65 nm CMOS design kit from ST Microelectronics are provided. An application example of the proposed delay line is provided for low-power, low-speed successive approximation register (SAR) analogue-to-digital converters (ADC).