Double cell upsets mitigation through triple modular redundancy. (February 2020) - Li, Yuanqing; Breitenreiter, Anselm; Andjelkovic, Marko; Chen, Junchao; Babic, Milan; Krstic, Milos
Abstract: A triple modular redundancy (TMR) based design technique for double cell upsets (DCUs) mitigation is investigated in this paper. This technique adds three extra self-voter circuits into a traditional TMR structure to enable the enhanced error correction capability. Fault-injection simulations show that the soft error rate (SER) of the proposed technique is lower than 3% of that of TMR. The implementation of this proposed technique is compatible with the automatic digital design flow, and its applicability and performance are evaluated on an FIFO circuit.