Extended Matrix Region Selection Code: An ECC for adjacent Multiple Cell Upset in memory arrays. (March 2020) - Silva, Felipe; Freitas, Walter; Silveira, Jarbas; Marcon, César; Vargas, Fabian
Abstract: With the widespread of electronics nowadays, Single Event Effects (SEEs) have become a significant concern, not only for critical applications like aerospace and military but also for the automotive industry and medical instruments, where reliability is always at a premium. This concern is notable in environments containing ElectroMagnetic (EM) and ionizing radiations, whose interactions with the matter may change the state of memory elements and thus, degrading system reliability. Technology scaling down increases the probability that the strike of a charged particle or a power bus fluctuation due to conducted EM interference affects more than one cell; therefore, resulting in a Multiple Cell Upset (MCU). Single Error Correction–Double Error Detection (SEC-DED) codes are among the most applied techniques to provide reliability to memory systems. However, standard implementations of SEC-DED codes are not suitable anymore to provide information reliability because they cannot satisfactorily handle a considerable number of bit-flips per coded word, i.e., MCU occurrence. In this context, this paper proposes the extended Matrix Region Selection Code (eMRSC), an improved version of MRSC, which extends the original 16-bit code previously published to a new MRSC version of 32 data bits. Additionally, it is proposed a new scheme of data matrix regions for reducing the number of generated redundant bits. The proposed codes were compared to well-known codes, presenting outperforms in all experiments. The synthesis analysis showed that the proposed codes are not only reliable, but they also result in low implementation cost (i.e., low area, coding/decoding delay and power overheads). Highlights: A low-cost Error Correction Code (ECC) to protect the memory information against Multiple Cell Upset (MCU) incidence. Two ECC formats proposed: one with higher error correction efficacy and another one with redundancy reduction. The proposed ECCs were compared with well-known techniques regarding correction efficacy, reliability, and synthesis cost. A correction per cost analysis of the proposed ECCs to evaluate the trade-off between error correction and synthesis cost.