An FPGA-based Priority Packet Queues. Issue 27 (2019)

• Record Type: Journal Article
• Authors: Smekal, David; Nemeth, Frantisek; Dvorak, Jan
• Is Part Of: IFAC-PapersOnLine. Volume 52:Issue 27(2019)
• Page Start: 377
• Page End: 381
• Publication Date: 2019
• Subjects: Packet Queues -- Quality of Service -- Shaping Throughput -- Limiter -- Tocken Bucket -- VHDL -- FPGA -- Netcope Development Kit; Automatic control -- Periodicals; 629.805
• DOI: 10.1016/j.ifacol.2019.12.689
• Languages: English
• ISSNs: 2405-8963

Abstract

Abstract: Paper deals with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In this paper, the design of limiter mechanism for Quality of Service (QoS) is performed. The article present the full description of the architecture, the simulation results and the results of the practical implementation on the NFB-200G2QL network cards based on the Xilinx Virtex UltraScale+ chip and works at 200 MHz. Various parameterized designs were synthesized to provide a comparative study with other implementations in FPGA technology.