Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic. (13th March 2020) - Goswami, Mrinal; Chattopadhyay, Subrata; Tripathi, Shiv Bhushan; Sen, Bibhash
The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.