0.6‐V CMOS cascode OTA with complementary gate‐driven gain‐boosting and forward body bias. (13th September 2019)

• Record Type: Journal Article
• Authors: Cellucci, Danilo; Centurelli, Francesco; Di Stefano, Valerio; Monsurrò, Pietro; Pennisi, Salvatore; Scotti, Giuseppe; Trifiletti, Alessandro
• Is Part Of: International journal of circuit theory and applications. Volume 48:Number 1(2020)
• Page Start: 15
• Page End: 27
• Publication Date: 2019-09-13
• Subjects: CMOS -- gain boosting -- low power -- low voltage -- OTA -- threshold lowering; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2703
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: An innovative low‐voltage low‐power complementary metal‐oxide‐semiconductor (CMOS) gain boosting approach is presented. It exploits complementary gate‐driven gain boosting and adopts forward body bias, resulting in the minimum possible supply requirement of one threshold plus two saturation voltages, without requiring any additional current branch. The solution is also exploited in a rail‐to‐rail high‐performance single‐stage cascode operational transconductance amplifier (OTA). Simulations using a 40‐nm process with thresholds around 0.45 V show that 0.6 V and 50 μA are adequate to supply the designed OTA, which exhibits a 60‐dB direct current (DC) gain, a 45‐MHz unity‐gain frequency, and an 18‐V/μs slew rate, under a 1‐pF load. Abstract : An innovative low‐voltage low‐power CMOS gain boosting approach is presented. It exploits complementary gate‐driven gain boosting and adopts forward body bias, resulting in the minimum possible supply voltage requirement. The solution is exploited to design a single‐stage cascode OTA in a 40‐nm CMOS process. It shows that 0.6V and 50 μA are adequate to supply the designed OTA, which exhibits a 60‐dB DC gain, a 45‐MHz unity‐gain frequency, and an 18‐V/μs slew rate under a 1‐pF load.