A 1‐bit full adder using CNFET based dual chirality high speed domino logic. (23rd December 2019)

• Record Type: Journal Article
• Authors: Garg, Sandeep; Gupta, Tarun K.; Pandey, Amit K.
• Is Part Of: International journal of circuit theory and applications. Volume 48:Number 1(2020)
• Page Start: 115
• Page End: 133
• Publication Date: 2019-12-23
• Subjects: CNFET -- Domino -- Dynamic -- FOM -- VLSI; Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2714
• Languages: English
• ISSNs: 0098-9886

Abstract

Abstract: CNFET devices are preferred over CMOS devices for designing high‐speed digital circuits. This paper introduces a new technique Dual Chirality High‐speed Domino Logic (DCHSDL) for implementing low power and high‐speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2‐input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1‐bit Full Adder designed using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1‐bit Full Adder. Abstract : A 1‐bit full adder using a new dual chirality based CNFET technique is proposed in this paper. The chirality indices of the transistors in the critical path is varied to improve the performance parameters of the proposed full adder circuit. Proposed full adder shows lower power consumption, higher speed and improved noise margin compared to existing circuits.