Strategy toward the fabrication of ultrahigh-resolution micro-LED displays by bonding-interface-engineered vertical stacking and surface passivation. Issue 48 (27th September 2019)

• Record Type: Journal Article
• Authors: Geum, Dae-Myeong; Kim, Seong Kwang; Kang, Chang-Mo; Moon, Seung-Hyun; Kyhm, Jihoon; Han, JaeHoon; Lee, Dong-Seon; Kim, SangHyeon
• Is Part Of: Nanoscale. Volume 11:Issue 48(2019)
• Page Start: 23139
• Page End: 23148
• Publication Date: 2019-09-27
• Subjects: Nanoscience -- Periodicals; Nanotechnology -- Periodicals; 620.505
• DOI: 10.1039/c9nr04423j
• Languages: English
• ISSNs: 2040-3364

Abstract

Abstract : In this study, we proposed a strategy to fabricate vertically stacked subpixel (VSS) micro-light-emitting diodes (μ-LEDs) for future ultrahigh-resolution microdisplays. Abstract : In this study, we proposed a strategy to fabricate vertically stacked subpixel (VSS) micro-light-emitting diodes (μ-LEDs) for future ultrahigh-resolution microdisplays. At first, to vertically stack the LED with different colors, we successfully adopted a bonding-interface-engineered monolithic integration method using SiO2 /SiN x distributed Bragg reflectors (DBRs). It was found that an intermediate DBR structure could be used as the bonding layer and color filter, which could reflect and transmit desired wavelengths through the bonding interface. Furthermore, the optically pumped μ-LED array with a pitch of 0.4 μm corresponding to the ultrahigh-resolution of 63 500 PPI could be successfully fabricated using a typical semiconductor process, including electron-beam lithography. Compared with the pick-and-place strategy (limited by machine alignment accuracy), the proposed strategy leads to the fabrication of significantly improved high-density μ-LEDs. Finally, we systematically investigated the effects of surface traps using time-resolved photoluminescence (TRPL) and two-dimensional simulations. The obtained results clearly demonstrated that performance improvements could be possible by employing optimal passivation techniques by diminishing the pixel size for fabricating low-power and highly efficient microdisplays.