Optimization of the interconnect resistance contribution for STT-MRAM technology. (January 2020)

• Record Type: Journal Article
• Authors: Dixit, Hemant; Narayanan, Sudarshan; Pfefferling, Bert; Mueller, Johannes
• Is Part Of: Microelectronics journal. Volume 95(2020)
• Publication Date: 2020-01
• Subjects: STT-MRAM -- TMR -- VIA -- Interconnects; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2019.104663
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: STT-MRAM has emerged as versatile memory technology, capable of serving a broad range of memory applications. A key figure of merit for the STT-MRAM device is the tunneling magnetoresistance ratio (TMR), which distinguishes between the high resistance ("Off") and low resistance ("On") state. In an Integrated Circuit (IC), the MRAM device is fabricated in back-end-of-line process and is powered using a MRAM Vertical Interconnect Access (M-VIA) structure. The series resistance from M-VIA structure, however, adversely impacts the TMR reducing the sense margin. Thus, to improve the TMR/sense margin of MRAM device, reduction of series M-VIA resistance is necessary. We present a combination of ab-initio & TCAD simulations to estimate the M-VIA resistance contributions. Advanced interconnect metals, which include Co, Ru and W, are studied with TiN as barrier metal. The role of barrier metal and geometry is systematically investigated. These simulations provide potential pathways to reduce the M-VIA resistance contributions, allowing for a high density MRAM array.