A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS. Issue 6 (3rd June 2019)

• Record Type: Journal Article
• Authors: Zhao, Long; Li, Bao; Cheng, Yuhua
• Is Part Of: International journal of electronics. Volume 106:Issue 6(2019)
• Page Start: 829
• Page End: 845
• Publication Date: 2019-06-03
• Subjects: Analog-to-digital converter (ADC) -- time-interleaved -- successive approximation register (SAR) -- design-for-test -- foreground calibration; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2019.1570557
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm 2, including the TI ADC core and memory.