An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing. Issue 6 (3rd June 2019)

• Record Type: Journal Article
• Authors: Ataie, Roghayeh; Emrani Zarandi, Azadeh Alsadat; Safaei Mehrabani, Yavar
• Is Part Of: International journal of electronics. Volume 106:Issue 6(2019)
• Page Start: 928
• Page End: 944
• Publication Date: 2019-06-03
• Subjects: Full Adder -- inexact -- CNFET -- PSNR -- Image Processing; Electronics -- Periodicals; Electronic control -- Periodicals; 621.381
• DOI: 10.1080/00207217.2019.1576232
• Languages: English
• ISSNs: 0020-7217

Abstract

ABSTRACT: The design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system's performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, power-delay product (PDP), energy-delay product (EDP), power-delay-area product (PDAP) and power-delay-area-PSNR product (PDAPP). Simulation results confirmed the superiority of the proposed Full Adder cells compared to others. For instance, the proposed 6TIFA improves PDAPP metric at least 21% and at most 76% compared to its counterparts at 0.9V power supply.