A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration. (12th August 2019)

• Record Type: Journal Article
• Authors: Bai, Xu; Yang, Jiajia; Dai, Qiong; Chen, Zhaolin
• Other Names: Li Gang guestEditor.; Batten Lynn guestEditor.; Foschini Luca guestEditor.; Kim Hyunbum guestEditor.; Dong Fang guestEditor.; Wu Chenshu guestEditor.; Gao Shangce guestEditor.
• Is Part Of: Concurrency and computation. Volume 31:Number 24(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-08-12
• Subjects: AES -- cluster -- hash -- heterogeneous -- RSA -- Zynq; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.5257
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Clusters based on hybrid architectures combining ARM CPUs and FPGA fabric, such as the Xilinx Zynq SoC, not only are energy‐efficient platforms with strong processing power but also have the advantages of distributed computing systems balancing the workload between cores, processors, and nodes. This paper employs a 48‐node cluster infrastructure based on the Xilinx Zynq SoC to accelerate classical cryptographic algorithms, including hash functions, AES, and RSA. In this design, we leverage the flexibility of the software to implement node‐to‐node communication through the message passing interface (MPI), and we offload the compute‐intensive tasks to the FPGA to accelerate complex calculations with the parallelizability of specific reconfigurable coprocessors. In addition, we study several parallel cryptography optimizations based on FPGA to evaluate this cluster. Finally, using a comparison with a multi‐core desktop (Intel i7‐3770) and a many‐core server (288 cores), the efficiency of the implementations of the selected data encryption and decryption algorithms is presented to illustrate the performance of our system; we also gain up to 3.6× increase in energy efficiency.