A study of the loops control for reconfigurable computing with OpenCL in the LABS local search problem. (January 2020)

• Record Type: Journal Article
• Authors: Russek, Paweł; Jamro, Ernest; Dąbrowska-Boruch, Agnieszka; Wiatr, Kazimierz
• Other Names: Cecilia José M guest-editor.
• Is Part Of: International journal of high performance computing applications. Volume 34:Number 1(2020)
• Page Start: 103
• Page End: 114
• Publication Date: 2020-01
• Subjects: Custom processors -- loops acceleration -- high-performance reconfigurable computing -- FPGA -- OpenCL -- LABS problem -- memetic algorithms; High performance computing -- Periodicals; Supercomputers -- Periodicals; 004.1105
• DOI: 10.1177/1094342019868515
• Languages: English
• ISSNs: 1094-3420

Abstract

In this article, we study the steepest descent local search (SDLS) algorithm that is used as the improvement step in the memetic algorithms for the search of low autocorrelation binary sequences (LABS). We address the method of reconfigurable computing, as the algorithm is of the field programmable gate array (FPGA) type as it features the integer operations, bit-wise data representation, regular execution flow, and huge computational complexity. It contains four levels of nested loops, but its direct parallel implementation as a custom processor leads to typical problems because the loops expose a dynamic range and too many iterations. This inhibits a simple parallel data path that is typically produced by the method of the loop unrolling. We have examined the four architectures that mitigate the found obstacles, and we provide the results of their implementation. The solutions take advantages of the loop pipelining, reordering of the loops, and dynamic reconfiguration. The recently available development tool was involved in our study as we have used the OpenCL (OCL) platform for FPGAs to draw practical conclusions. The given proposals are characterized by their performance and capacity for a problem size. Consequently, the speed/size trade-off is highlighted, as an FPGA size is a design constraint. The performance of the FPGA-based solutions is compared to the CPU speed, and the maximum reported speed-up is 750. Readers can further develop and/or use the presented OCL solutions for efficient LABS discovery as we provide the corresponding software repository.