Analysis of Deep Level and Oxide Interface Defects Using 100V HF Schottky Diodes and MOS CV for Silicon and 4H SiC HV MOSFETs, Advanced Power Electronics, and RF ASIC. (2019)

• Record Type: Journal Article
• Authors: Pan, J; Afroz, S.; Crain, N.; Henning, W.; Oliver, J.; Knight, T.
• Is Part Of: MRS advances. Volume 4:Number 44/45(2019)
• Page Start: 2377
• Page End: 2382
• Publication Date: 2019
• Subjects: dielectric, -- dielectric properties, -- electronic material, -- microelectronics, -- oxidation; Electrical engineering -- Congresses; Physics -- Congresses; Materials -- Research -- Congresses; Materials science -- Congresses; 620.11
• DOI: 10.1557/adv.2019.224
• Languages: English
• ISSNs: 2059-8521

Abstract

Abstract: In this paper we report high voltage MOS and Schottky Diode CV techniques for silicon and SiC power devices. 4H Silicon carbide is a wide bandgap semiconductor suitable for high voltage power electronics and RF applications due to high avalanche breakdown critical electric field, and thermal conductivity. The performance of various power devices, which may include MOSFET and Static Induction Transistor (SIT), can be affected by the deep level traps in the substrate and the oxide interfacial defects. We have characterized deep level trap (High Voltage Schottky Diode HF CV) and oxide interface trap densities (High Voltage HF MOS CV), measured the device channel doping profile for both 4H SiC and silicon, gate metal workfunction, and simulated the effects on DC/AC performance.