Enabling shared memory communication in networks of MPSoCs. (25th September 2018)

• Record Type: Journal Article
• Authors: Lant, Joshua; Concatto, Caroline; Attwood, Andrew; Pascual, Jose A.; Ashworth, Mike; Navaridas, Javier; Luján, Mikel; Goodacre, John
• Other Names: Xiang Yang guestEditor.; Alam Bhuiyan Md Zakirul guestEditor.; Castiglione Aniello guestEditor.; Wang Yu guestEditor.; Shen Hong guestEditor.; Tian Hui guestEditor.; Sang Yingpeng guestEditor.; Acacio Manuel E. guestEditor.; Sahuquillo Julio guestEditor.
• Is Part Of: Concurrency and computation. Volume 31:Number 21(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2018-09-25
• Subjects: distributed shared memory -- FPGA -- HPC -- interconnect -- MPSoC -- networks; Parallel processing (Electronic computers) -- Periodicals; Parallel computers -- Periodicals; 004.35
• DOI: 10.1002/cpe.4774
• Languages: English
• ISSNs: 1532-0626

Abstract

Summary: Ongoing transistor scaling and the growing complexity of embedded system designs has led to the rise of MPSoCs (Multi‐Processor System‐on‐Chip), combining multiple hard‐core CPUs and accelerators (FPGA, GPU) on the same physical die. These devices are of great interest to the supercomputing community, who are increasingly reliant on heterogeneity to achieve power and performance goals in these closing stages of the race to exascale. In this paper, we present a network interface architecture and networking infrastructure, designed to sit inside the FPGA fabric of a cutting‐edge MPSoC device, enabling networks of these devices to communicate within both a distributed and shared memory context, with reduced need for costly software networking system calls. We will present our implementation and prototype system and discuss the main design decisions relevant to the use of the Xilinx Zynq Ultrascale+, a state‐of‐the‐art MPSoC, and the challenges to be overcome given the device's limitations and constraints. We demonstrate the working prototype system connecting two MPSoCs, with communication between processor and remote memory region and accelerator. We then discuss the limitations of the current implementation and highlight areas of improvement to make this solution production‐ready.