A high‐performance CMOS four‐stage amplifier. (1st July 2019)

• Record Type: Journal Article
• Authors: Soltani Zanjani, Masoud; Asiyabi, Tayebeh; Biabanifard, Sadegh
• Other Names: Soh Ping Jack guestEditor.
• Is Part Of: International journal of numerical modelling. Volume 32:Number 6(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-07-01
• Subjects: CMOS amplifier -- frequency compensation -- low die area -- Miller effect -- pole‐zero cancelation -- symbolic transfer function; Electric networks -- Mathematical models -- Periodicals; Electronics -- Mathematical models -- Periodicals; 621.3011
• DOI: 10.1002/jnm.2647
• Languages: English
• ISSNs: 0894-3370

Abstract

Abstract: In this paper, we theoretically propose and mathematically describe an effective four‐stage structure in Complementary metal‐oxide‐semiconductor (CMOS) technology based on differential block feedback. The special architecture of frequency compensation network improves frequency response with very small value of compensation capacitor, which results in low die area occupation. The presented novel and simple four‐stage structure is frequency compensated just via single Miller capacitor and a differential block. Symbolical transfer function is calculated, and circuit dynamics are introduced. To well explain theoretical description, the proposed configuration at circuit level is simulated using Taiwan Semiconductor Manufacturing Company Limited (TSMC) 0.18‐μm CMOS technology and HSPICE circuit simulator. The proposed configuration and corresponding circuit benefits from circuit simplicity and low die‐area occupation. The frequency compensation network forms two Miller loops with negative loop gains. Feedback paths are amplified via differential block while feedforward paths are attenuated, leads to improving frequency response compare with conventional structures. Ample simulation results are in good agreement with theoretical description. Leveraging the concept and method proposed four‐stage amplifier exhibits 170 dB, 8.12 MHz, and 90° as direct current (DC) gain, Gain‐BandWidth Product (GBW), and Pase Margin (PM), respectively. The supply voltage is set to 1.8 V, while the simulated circuit consumes 380 μW.