Active load with cross‐coupled bulk for high‐gain high‐CMRR nanometer CMOS differential stages. (22nd July 2019) - Ballo, Andrea; Grasso, Alfio D.; Pennisi, Salvatore
Summary: Nanometer CMOS technologies are characterized by low intrinsic gain and limited rejection to common‐mode disturbances, issues that analog designers must counteract through nonconventional circuit solutions able to operate under sub–1‐V supply voltages. In this letter, an approach originally proposed as a common‐mode control loop for body‐driven amplifiers is exploited by cross‐connecting the bulk terminals of the active‐load transistors of a source‐coupled pair to sensibly improve its small‐signal performance. A design example in 65‐nm process supplied from 750 mV shows that the presented solution offers both a nominal 20‐dB increase in differential gain and 29‐dB increase in CMRR, as compared with the standard counterpart. Abstract : Nanometer CMOS technologies suffer from low intrinsic gain and limited rejection to common‐mode disturbances. Based on a previous paper, an approach is discussed that exploits the bulk terminal of the active‐load transistors of differential pair to sensibly improve its small‐signal performance. A design example in 65‐nm process supplied from 750 mV shows that the proposed solution offers both a 20‐dB increase in differential gain and a 29‐dB increase in CMRR, as compared with the standard solution.