Optimal True Time Delay Filter With Application to FPGA Firmware‐Based Phased Array Radar Signal Processing. Issue 9 (5th September 2019)

• Record Type: Journal Article
• Authors: Lehtinen, Markku; Damtie, Baylie; Orispää, Mikko
• Is Part Of: Radio science. Volume 54:Issue 9(2019)
• Page Start: 810
• Page End: 821
• Publication Date: 2019-09-05
• Subjects: incoherent scatter -- radar signal -- ionosphere -- signal processing; Radio meteorology -- Periodicals; Radio wave propagation -- Periodicals; 621.38405
• DOI: 10.1029/2019RS006821
• Languages: English
• ISSNs: 0048-6604

Abstract

Abstract: The European Incoherent Scatter‐3D phased array radar system will be largely based on field‐programmable gate array (FPGA) firmware electronics that carry out the signal processing by using different digital filters. In this paper we have presented a method of designing an optimal true time delay finite impulse response filter with applications to an FPGA firmware‐based multichannel signal processing system. The method provides an optimal true time delay finite impulse response filter with the desired responses at both band pass and stopband. This is possible by finding a mathematical minimization solution for the total power of all filter coefficients longer than a prespecified half‐length. The analysis is based on freely choosing the responses in the transition band until user‐specified desired responses are achieved. We have investigated the performance of these optimal digital filters in terms of the required digital signal processing (DSP) resources in GMACs (giga multiply accumulates per second) by considering both all‐in‐one stage filtering and cascaded solutions for ion and plasma line incoherent scatter radar measurements. We have shown that the cascaded solution provides more efficient utilization of DSP resources and hence represents the optimal choice for processing the proposed European Incoherent Scatter‐3D phased array radar signals. An example is demonstrated in which 906.88 GMACs are required to process 208 ion line beams with 2×4‐bit resolution in all‐in‐one stage processing, as compared to the 79.16 GMACs needed for a similar task in a cascaded solution. Key Points: A method of designing true time delay filter is presented All‐in‐one and cascaded arrangement is formulated Cascaded filtering saves DSP resources when compared with all‐in‐one filtering operation