A 15‐MHz bandwidth double sampling MASH25b‐15b sigma‐delta modulator with DEM for multibit DACs. (25th July 2019)

• Record Type: Journal Article
• Authors: Li, Di; Fei, Chunlong; Zhang, Qidong; Li, Yani; Wu, Xiaopeng; Yang, Yintang
• Is Part Of: International journal of circuit theory and applications. Volume 47:Number 10(2019)
• Page Start: 1555
• Page End: 1567
• Publication Date: 2019-07-25
• Subjects: dynamic element matching (DEM) -- effective number of bits (ENOB) -- multistage noise shaping (MASH) -- sigma‐delta modulator -- signal‐to‐noise and distortion ratio (SNDR); Electric circuit analysis -- Periodicals; 621.319205
• DOI: 10.1002/cta.2679
• Languages: English
• ISSNs: 0098-9886

Abstract

Summary: A high SNDR discrete‐time (DT) 2‐1 MASH sigma‐delta modulator (SDM) for 15‐MHz bandwidth was presented. Cascade of integrators with feedforward (CIFF) scheme, combined with the optimized gain coefficients, was adopted to avoid of the integrators. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. Five‐bit flash quantizer was adopted in both stages to improve the overall signal‐to‐noise and distortion ratio (SNDR) performance, and third‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated in a mature 0.18‐μm CMOS technology, the occupied area of the modulator was 0.24 mm 2 and dissipation power 25.4 mW from a 1.8‐V voltage supply. As a sampling rate of 240 MHz for the input sampling and DAC and 480 MHz for the flash ADC, a SNDR of 90.2 dB over 15‐MHz signal bandwidth and the corresponding effective number of bits (ENOB) of 14.69 bit were achieved. The spurious‐free dynamic range (SFDR) was 98 dB with DEM turned on for a 3.75 MHz at −2.5‐dBFS input signal, and the figure of merit (FOM) was 30.7 fJ/conv. for 15‐MHz bandwidth. A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency and therefore reduce the power consumption. High‐order DEM was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on. Abstract : A 15‐MHz bandwidth multibit MASH2‐1 discrete‐time sigma‐delta modulator was proposed. Double sampling technique was employed to relax the OPA settling requirements by halving the clock frequency, and therefore reduce the power consumption. High‐order dynamic element matching (DEM) was analyzed and applied for the multibit DACs to suppress the element mismatch noise. Fabricated by a 0.18‐μm CMOS process, the modulator achieved a SNDR of 90.2 dB and the corresponding ENOB 14.69 bit over 15‐MHz signal bandwidth. The proposed modulator was very suitable for wideband applications including wireless communication systems, high‐frequency biomedical imaging or sensing systems, and so on.