CMOS rectifier design for RFID chip with high sensitivity at low input power to be combined with an ultrasmall antenna. (10th May 2019)

• Record Type: Journal Article
• Authors: Jantarachote, Vasan; Tontisirin, Sitt; Akkaraekthalin, Prayoot; Negra, Renato; Chalermwisutkul, Suramate
• Other Names: Soh Ping Jack guestEditor.
• Is Part Of: International journal of numerical modelling. Volume 32:Number 6(2019)
• Page Start: n/a
• Page End: n/a
• Publication Date: 2019-05-10
• Subjects: CMOS RF rectifier -- leakage current -- micropower rectifier -- power conversion efficiency -- sensitivity -- threshold compensation; Electric networks -- Mathematical models -- Periodicals; Electronics -- Mathematical models -- Periodicals; 621.3011
• DOI: 10.1002/jnm.2607
• Languages: English
• ISSNs: 0894-3370

Abstract

Abstract: This paper presents CMOS radio frequency (RF) rectifier circuit design for radio frequency identification (RFID) tag with integrated on‐chip antenna. The proposed design focuses on high sensitivity and high efficiency at low input power. The rectifier circuit was designed using Advanced Design System (ADS) software tool with the UMC130 process as a single‐ended rectifier structure in different topologies where sensitivity and efficiency enhancement techniques are applied. This work presents the performance of the proposed CMOS RF rectifier circuit in comparison with previously published works for 915 MHz and 5.8 GHz operating frequencies. For the 915 MHz band, the highest sensitivity of −19.8 dBm is provided by the adaptive threshold voltage compensation circuit with a power conversion efficiency of 9.843%. The 5.8 GHz band uses the adaptive threshold voltage compensation and dynamic bulk bias techniques providing the highest sensitivity of −16.8 dBm. Compared with other works in the literature, the proposed circuits offer greater sensitivity and can easily be matched with ultrasmall on‐chip antennas because of appropriate values of the input impedance.