Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications. (October 2019)

• Record Type: Journal Article
• Authors: Bhuvana, B.P.; Kanchana Bhaaskaran, V.S.
• Is Part Of: Microelectronics journal. Volume 92(2019)
• Publication Date: 2019-10
• Subjects: Adiabatic logic -- Energy recovery circuit -- FinFET-based circuit design -- Low power circuit design -- Adder; Microelectronics -- Periodicals; Microélectronique -- Périodiques; Microelectronics; Electronic journals; Journals - contents and abstracts; Periodicals; 621.3805
• DOI: 10.1016/j.mejo.2019.104601
• Languages: English
• ISSNs: 0959-8324

Abstract

Abstract: This paper presents FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation. Differential cascode adiabatic logic and pass transistor structure are employed. Furthermore, EEPAL employs discharge transistors assisting in eliminating floating output nodal issues of existing adiabatic circuits. Its efficiency is proved through half and full adder circuits constructed using FinFET-based 2N2P, 2N2N2P, Positive Feedback Adiabatic Logic (PFAL), Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) and Pass transistor Adiabatic Logic (PAL) based circuits. Carry Lookahead Adder (CLA) and Carry Save Multiplier (CSM) are used as benchmark circuits to validate the efficiency of EEPAL. Energetics of EEPAL and effect of parameter variations on energy dissipation have been derived and analyzed. BSIMCMG FinFET models have been used for simulations in Cadence® Virtuoso. At 500 MHz, 16-bit CSM designed using EEPAL is 25%, 34%, 21% and 12% energy efficient than CSM designed using 2N2P, 2N2N2P, PFAL and DCPAL.