Thermal management challenges and mitigation techniques for transistor-level 3-D integration. (September 2019) - Iqbal, Md Arif; Macha, Naveen Kumar; Danesh, Wafi; Hossain, Sehtab; Rahman, Mostafizur
Abstract: For beyond 2-D CMOS logic, transistor-level 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] hold the most promise. However, such 3-D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as additional thermal resistance imposed by vertical layer stacking escalate the temperature, especially for the layers that are far detached from the substrate. Traditional system-level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor-level 3-D integrations and have huge cost overhead [7]. Previously, we introduced the concept of heat management in 3-D ICs through architecting physical fabric features [8]. In this paper, we elaborate on the thermal management approach, show its application for emerging transistor-level 3-D ICs through Finite Ele ment Method (FEM) based modeling and simulations, quantify results and compare for various scenarios. The modeling approach accounts for details of the 3-D device structure, nanoscale material properties, and 3-D circuit operations. The simulations were performed for both static and transient scenarios. Our simulation results show that without any heat extraction feature, the temperature for monolithic 3-D, Skybridge and SN3D, can be increased by almost 100 K, 200 K & 20 K, respectively. However, the proposed heat extraction feature is very effective in heat management, reducing the temperature from the heated area by up to 175 K, 320 K, and 20 K for monolithic 3-D, Skybridge and SN3D, respectively.