Thermal management challenges and mitigation techniques for transistor-level 3-D integration. (September 2019)
- Record Type:
- Journal Article
- Title:
- Thermal management challenges and mitigation techniques for transistor-level 3-D integration. (September 2019)
- Main Title:
- Thermal management challenges and mitigation techniques for transistor-level 3-D integration
- Authors:
- Iqbal, Md Arif
Macha, Naveen Kumar
Danesh, Wafi
Hossain, Sehtab
Rahman, Mostafizur - Abstract:
- Abstract: For beyond 2-D CMOS logic, transistor-level 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] hold the most promise. However, such 3-D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as additional thermal resistance imposed by vertical layer stacking escalate the temperature, especially for the layers that are far detached from the substrate. Traditional system-level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor-level 3-D integrations and have huge cost overhead [7]. Previously, we introduced the concept of heat management in 3-D ICs through architecting physical fabric features [8]. In this paper, we elaborate on the thermal management approach, show its application for emerging transistor-level 3-D ICs through Finite Ele ment Method (FEM) based modeling and simulations, quantify results and compare for various scenarios. The modeling approach accounts for details of the 3-D device structure, nanoscale material properties, and 3-D circuit operations. The simulations were performed for both static and transient scenarios. Our simulation results show that without any heat extraction feature, the temperature for monolithic 3-D, Skybridge and SN3D, can be increased by almost 100 K, 200 K & 20 K, respectively. However, the proposed heat extraction feature is very effective in heat management, reducing theAbstract: For beyond 2-D CMOS logic, transistor-level 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] hold the most promise. However, such 3-D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as additional thermal resistance imposed by vertical layer stacking escalate the temperature, especially for the layers that are far detached from the substrate. Traditional system-level approaches such as liquid cooling [5], heat spreader [6], etc. are inadequate for transistor-level 3-D integrations and have huge cost overhead [7]. Previously, we introduced the concept of heat management in 3-D ICs through architecting physical fabric features [8]. In this paper, we elaborate on the thermal management approach, show its application for emerging transistor-level 3-D ICs through Finite Ele ment Method (FEM) based modeling and simulations, quantify results and compare for various scenarios. The modeling approach accounts for details of the 3-D device structure, nanoscale material properties, and 3-D circuit operations. The simulations were performed for both static and transient scenarios. Our simulation results show that without any heat extraction feature, the temperature for monolithic 3-D, Skybridge and SN3D, can be increased by almost 100 K, 200 K & 20 K, respectively. However, the proposed heat extraction feature is very effective in heat management, reducing the temperature from the heated area by up to 175 K, 320 K, and 20 K for monolithic 3-D, Skybridge and SN3D, respectively. … (more)
- Is Part Of:
- Microelectronics journal. Volume 91(2019)
- Journal:
- Microelectronics journal
- Issue:
- Volume 91(2019)
- Issue Display:
- Volume 91, Issue 2019 (2019)
- Year:
- 2019
- Volume:
- 91
- Issue:
- 2019
- Issue Sort Value:
- 2019-0091-2019-0000
- Page Start:
- 61
- Page End:
- 69
- Publication Date:
- 2019-09
- Subjects:
- Transistor-level 3-D integration -- Finite element model -- Transient thermal behavior -- Thermal management -- Intrinsic fabric feature
Microelectronics -- Periodicals
Microélectronique -- Périodiques
Microelectronics
Electronic journals
Journals - contents and abstracts
Periodicals
621.3805 - Journal URLs:
- http://catalog.hathitrust.org/api/volumes/oclc/5877621.html ↗
http://www.sciencedirect.com/science/journal/00262692 ↗
http://www.intute.ac.uk/sciences/cgi-bin/fullrecord.pl?handle=lesa.1012319367 ↗
http://www.elsevier.com/journals ↗
http://www.elsevier.com/homepage/elecserv.htt ↗ - DOI:
- 10.1016/j.mejo.2019.07.004 ↗
- Languages:
- English
- ISSNs:
- 0959-8324
- Deposit Type:
- Legaldeposit
- View Content:
- Available online (eLD content is only available in our Reading Rooms) ↗
- Physical Locations:
- British Library DSC - 5758.973000
British Library DSC - BLDSS-3PM
British Library HMNTS - ELD Digital store - Ingest File:
- 11630.xml