Monte Carlo Processing on a Chip (MCoaC)-preliminary experiments toward the realization of optimal-hardware for TOPAS/Geant4 to drive discovery. (August 2019) - Abhyankar, Yogindra S.; Dev, Sachin; Sarun, O.S.; Saxena, Amit; Joshi, Rajendra; Darbari, Hemant; Sajish, C.; Sonavane, U.B.; Gavane, Vivek; Deshpande, Abhay; Dixit, Tanuja; Harsh, Rajesh; et al.
Highlights: Field programmable gate arrays (FPGAs) can linearly speed code by 200 fold each. We are attempting to use FPGAs to speed up Geant4 calculations. FPGAs scale, use little power, and have high precision. We show the issues involved in porting Geant4 to FPGA code and possible solutions. Abstract: Amongst the scientific frameworks powered by the Monte Carlo (MC) toolkit Geant4 (Agostinelli et al., 2003), the TOPAS (Tool for Particle Simulation) (Perl et al., 2012) is one. TOPAS focuses on providing ease of use, and has significant implementation in the radiation oncology space at present. TOPAS functionality extends across the full capacity of Geant4, is freely available to non-profit users, and is being extended into radiobiology via TOPAS-nBIO (Ramos-Mendez et al., 2018). A current "grand problem" in cancer therapy is to convert the dose of treatment from physical dose to biological dose, optimized ultimately to the individual context of administration of treatment. Biology MC calculations are some of the most complex and require significant computational resources. In order to enhance TOPAS's ability to become a critical tool to explore the definition and application of biological dose in radiation therapy, we chose to explore the use of Field Programmable Gate Array (FPGA) chips to speedup the Geant4 calculations at the heart of TOPAS, because this approach called "Reconfigurable Computing" (RC), has proven able to produce significant (around 90x) (Sajish et al., 2012) speed increases in scientific computing. Here, we describe initial steps to port Geant4 and TOPAS to be used on FPGA. We provide performance analysis of the current TOPAS/Geant4 code from an RC implementation perspective. Baseline benchmarks are presented. Achievable performance figures of the subsections of the code on optimal hardware are presented; Aspects of practical implementation of "Monte Carlo on a chip" are also discussed.