Optimizing MOS-gated thyristor using voltage-based equivalent circuit model for designing steep-subthreshold-slope PN-body-tied silicon-on-insulator FET. (2nd March 2018)

• Record Type: Journal Article
• Authors: Ueda, Daiki; Takeuchi, Kiyoshi; Kobayashi, Masaharu; Hiramoto, Toshiro
• Is Part Of: Japanese journal of applied physics. Volume 57:Number 4(2018)Supplement
• Publication Date: 2018-03-02
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.57.04FD06
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: A new circuit model that provides a clear guide on designing a MOS-gated thyristor (MGT) is reported. MGT plays a significant role in achieving a steep subthreshold slope of a PN-body tied silicon-on-insulator (SOI) FET (PNBTFET), which is an SOI MOSFET merged with an MGT. The effects of design parameters on MGT and the proposed equivalent circuit model are examined to determine how to regulate the voltage response of MGT and how to suppress power dissipation. It is demonstrated that MGT with low threshold voltages, small hysteresis widths, and small power dissipation can be designed by tuning design parameters. The temperature dependence of MGT is also examined, and it is confirmed that hysteresis width decreases with the average threshold voltage kept nearly constant as temperature rises. The equivalent circuit model can be conveniently used to design low-power PNBTFET.