Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application. (5th March 2018)

• Record Type: Journal Article
• Authors: Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro
• Is Part Of: Japanese journal of applied physics. Volume 57:Number 4(2018)Supplement
• Publication Date: 2018-03-05
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.57.04FD08
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.