Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure. (19th February 2018)

• Record Type: Journal Article
• Authors: Yoon, Young Jun; Seo, Jae Hwa; Man Kang, In
• Is Part Of: Japanese journal of applied physics. Volume 57:Number 4(2018)Supplement
• Publication Date: 2018-02-19
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.57.04FG03
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length ( L G2_D-underlap ) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).