CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits. (16th March 2018)

• Record Type: Journal Article
• Authors: Litta, Eugenio Dentoni; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O'Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto
• Is Part Of: Japanese journal of applied physics. Volume 57:Number 4(2018)Supplement
• Publication Date: 2018-03-16
• Subjects: Physics -- Periodicals; 621.05
• DOI: 10.7567/JJAP.57.04FB08
• Languages: English
• ISSNs: 0021-4922

Abstract

Abstract: Integration of high- k /metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high- k /metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.