Capacitor current imbalance and its suppression method between phase legs for three‐phase inverter. Issue 4 (10th January 2019)

• Record Type: Journal Article
• Authors: Hirao, Takashi; Wada, Keiji; Shimizu, Toshihisa
• Is Part Of: Electrical engineering in Japan. Volume 206:Issue 4(2019)
• Page Start: 45
• Page End: 54
• Publication Date: 2019-01-10
• Subjects: current imbalance -- DC‐link capacitor -- resonance -- stray inductance -- switching frequency; Electrical engineering -- Periodicals; 621.30952
• DOI: 10.1002/eej.23160
• Languages: English
• ISSNs: 0424-7760

Abstract

Abstract: This paper proposes a method to suppress the capacitor current imbalance between the phase legs of a three‐phase inverter circuit. This circuit consists of half‐bridge modules and DC‐link capacitors closely connected to each module. It can be designed for low stray inductance between power semiconductor devices and DC‐link capacitors in each module. However, in the conventional structure, the stray inductance between the phase legs may lead to an imbalance in the capacitor current due to the DC‐side resonance phenomenon under a higher switching frequency condition by using a SiC MOSFET. This paper presents the analyses of the equivalent circuit considering the circuit configuration, which suggests that capacitor current imbalance occurs depending on the stray inductance between phase legs. To suppress the capacitor current imbalance, a delta‐type bus bar connecting phase legs is proposed. The experiment results at 300 V and 4.6 A demonstrate the suppression effectiveness of the proposed method.