Phosphorene source engineered stacked metal gate tunnel field effect transistor with enhanced scaling. (December 2018) - Kumar, Mirgender; Seong, Kwang-Su; Park, Si-Hyun
Abstract: In this simulation based study, we report a tunnel field effect transistor on SOI substrates with phosphorene as source material to enhance the scaling of Si CMOS technology. The proposed device has been evaluated in the form of two design concept (lateral as well as vertical tunneling) and compared with its counterpart of Germanium source and silicon based conventional devices. Electrostatic doping is utilized in place of conventional chemical doping in the active medium, source and drain. This heterostructure tunnel FETs boots the conduction current significantly and reduced the supply voltage by unique thickness dependent properties of phosphorene. The proposed TFET found a wonderful energy efficient (10 −2  fJ switching energy) steep switching device (∼0.1 mV/dec of point subthreshold swing) for future CMOS scaling with ∼10 9 on-to-off current ratio with 150 mV gate voltage swing and expected for sub-0.2 V operation at ≥1 GHz frequency. Highlights: This simulation study proposed a novel phosphorene source Tunnel FETs. The device has been evaluated with lateral as well as vertical tunneling design. The proposed Tunnel FET found energy efficient with 10 −2  fJ switching energy. The device shows 0.1 mV/dec SS with ∼10 9 Ion/Ioff for 150 mV gate voltage swing. The device will be expected for sub-0.2 V operation at ≥1 GHz frequency.