An efficient pathfinding system in FPGA for edge/fog computing. (15th May 2019)

• Record Type: Journal Article
• Authors: Nery, Alexandre Solon; Sena, Alexandre Da Costa; Guedes, Leandro S.
• Is Part Of: International journal of grid and utility computing. Volume 10:Number 3(2019)
• Page Start: 212
• Page End: 223
• Publication Date: 2019-05-15
• Subjects: pathfinding -- FPGA accelerator -- high-level synthesis -- fog computing -- edge computing; Electronic data processing -- Distributed processing -- Periodicals; Electronic commerce -- Management -- Computer programs -- Periodicals; 004.605
• Languages: English
• ISSNs: 1741-847X

Abstract

Pathfinding algorithms are at the heart of several classes of applications, such as network appliances (routing) and autonomous vehicle navigation. Thus, this work aims at designing and evaluating an efficient pathfinding FPGA accelerator based on Dijkstra's shortest path algorithm to mitigate the increasing network traffic problem at the edge of the network. The system is designed using Xilinx High-Level Synthesis (HLS) compiler and is implemented in the programming logic of a Xilinx Zynq FPGA, embedded with an ARM microprocessor which is not only in charge of controlling the co-processor but also in charge of lightweight TCP/IP network communication. Extensive performance, circuit-area, and energy consumption results show that the co-processor can find the shortest path about 2.5 times faster than the system's ARM microprocessor, on a simulation scenario test case based on touristic locations in the city of Rio de Janeiro, acquired from the OpenStreetMap database.